As the demand for integrated circuits having ever-smaller device features continues to increase, challenges to meet this demand must be met. As device features continue to decrease in size, resistance-capacitance (RC) delay in metal interconnects of devices remains an obstacle to improving computing performance. To support further increases in transistor density, either conductor resistance or dielectric capacitance must decrease. Whereas copper has been the conductor material of choice for interconnects since the introduction of the dual damascene process in the late 1990's, the pursuit of new low-dielectric-constant (‘low-k’) materials to replace traditional SiO2 (k≈4) has remained a priority in the semiconductor industry for decades.
Several types of low-k dielectrics exist. Types of low-k dielectrics include the bulk inter/intra-layer dielectric (ILD), which has the most stringent requirements on k, as well as dielectric diffusion barriers, etch stop layers, hard masks, and spacer layers, which have more modest k requirements but additional performance metrics that must be met.
Low-k materials have steadily improved, with the most recent introduction of porous SiOC:H variants (k=2.4-2.7) for ILDs and SiC:H (k=4.0-7.0) and SiCN:H (k=4.5-5.8) as diffusion barrier materials. An additional challenge, however, includes the difficulty in simultaneously maintaining chemical, thermal, electrical, and mechanical reliability. As a result, as dielectric needs are met through the engineering of a given dielectric material, the chemical, thermal and/or mechanical characteristics of that dielectric material in many cases suffer. For example, the falloff in mechanical properties with decreasing k, dubbed the ‘low-k death curve,’ is one of the key obstacles to further improvements in ultra-low-k ILD materials. Therefore, it would be desirable to provide a method of forming an improved dielectric material, which serves as an alternative to silicon-based materials for interconnect dielectric applications.